SYSTOLIC REALIZATION OF DELAYED 2-PATH LINEAR-PHASE FIR DIGITAL-FILTERS

A new method for high speed realisation of 1-dimensional (1D) linear p hase FIR digital filter is presented. The method makes use of pipelini ng in systolic arrays to reduce the minimum clock cycle time, the dela yed two-path structure to increase processing speed, and the symmetry of coefficients in a linear phase FIR digital filter to reduce multipl ications. The resultant systolic delayed two-path digital filter struc ture is consisted of four systolic arrays built from one type of basic cells with nearest neighbour interconnections. The method is optimal in terms of the number of multiplications. Both input and output of th e proposed filter structure can also be systolised to form an overall pure systolic structure. The proposed digital filter structure can pro vide a speed improvement of 32 times as compared to that of a direct r ealisation of the same filter using a single processor. The proposed m ethod is attractive for high speed adaptive and nonadaptive digital fi ltering.