The single-event upset (SEU) characteristics of GaAs devices and circu
its are reviewed. GaAs FET-based integrated circuits (IC's) are suscep
tible to upsets from both cosmic-ray heavy ions and protons trapped in
the Earth's radiation belts. The origin of the SEU sensitivity of GaA
s IC's is discussed in terms of both device-level and circuit-level co
nsiderations. At the device level, efficient charge-enhancement mechan
isms through which more charge can be collected than is deposited by t
he ion have a significant negative impact on the SEU characteristics o
f GaAs IC's. At the circuit level, different GaAs digital logic topolo
gies exhibit different levels of sensitivity to SEU because of variati
ons in parameters, including logic levels, capacitances, and the degre
e of gate or peripheral isolation. The operational and SEU characteris
tics of several different GaAs logic families are discussed. Recent ad
vances in materials and processing that provide possible solutions to
the SEU problem are addressed.