EXPERIMENTAL REALIZATION OF A 2-DIMENSIONAL TO 2-DIMENSIONAL TUNNEL TRANSISTOR

We report on the fabrication of an InP-based two-dimensional to two-di mensional tunnel transistor with two modulation-doped strained In0.75G a0.25As quantum wells of different thickness. The channels are separat ed by a 10 nm thick InP barrier. Source and drain contacts are realize d by non-alloyed ohmic contacts to the upper strained InGaAs layer wit hout short circuit to the second layer. An (NH4)(2)S passivation techn ique was used to minimize the interface state density and to enable ga te control through a SiO2 gate oxide. Below 120 K the transistor shows distinct tunnel effects. The drain current has a negative differentia l resistance at high gate voltages with a peak to valley ratio bf up t o 3.7, whereas at low gate voltages a sudden increase of the drain cur rent by a factor of 2.8 can be observed at a certain gate voltage.