BEHAVIORAL MODELING PHASE-LOCKED LOOPS FOR MIXED-MODE SIMULATION

Citation
Baa. Antao et al., BEHAVIORAL MODELING PHASE-LOCKED LOOPS FOR MIXED-MODE SIMULATION, Analog integrated circuits and signal processing, 10(1-2), 1996, pp. 45-65
Citations number
39
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
ISSN journal
09251030
Volume
10
Issue
1-2
Year of publication
1996
Pages
45 - 65
Database
ISI
SICI code
0925-1030(1996)10:1-2<45:BMPLFM>2.0.ZU;2-I
Abstract
Phase-locked Loops(PLLs) are a class of feedback systems with wide ran ge of applications. A PLL in its entirety can be viewed as a closed-lo op servosystem, comprised of three major functional subsystems; 1) Pha se detectors, 2) Loop filters and 3) Voltage/Current controlled oscill ators. The overall characteristics of the phase-locked loop are depend ent on the realization of individual subsystems which have mixed analo g-digital implementations. In simulating a PLL, one has to deal with t he mixed-signal nature of most implementations, as well as the problem of simulating the PLL over a large number of signal cycles. Long simu lation run times plague the simulation of a PLL using a conventional s imulator, sometimes making such simulation impractical. In the methodo logy described in this paper, these drawbacks are overcome by the use of behavioral models and a mixed-signal simulation platform. This pape r presents a general mixed-mode behavioral simulation methodology and the derivation of behavioral simulation models for various kinds of PL Ls. The top-down and bottom-up modeling paradigms are illustrated thro ugh the use of examples of actual PLL designs. The simulation models a re generated for the AT&T Bell Laboratories mixed analog-digital simul ator, ATTSIM.