HIERARCHICAL FAULT MODELING FOR LINEAR ANALOG CIRCUITS

This paper presents a hierarchical fault modeling approach for catastr ophic as well as out-of-specification (parametric) faults in analog ci rcuits. These include both, ac and de faults in passive as well as act ive components. The fault models are based on functional error charact erization. Case studies based on CMOS and nMOS operational amplifiers are discussed, and a full listing of derived behavioral fault models i s presented. These fault models are then mapped to the faulty behavior at the macro-circuit level. Application of these fault models in an e fficient fault simulator for analog circuits is also described.