PROGRAMMABLE-WEIGHT BUILDING-BLOCKS FOR ANALOG VLSI NEURAL-NETWORK PROCESSORS

Although the neural network paradigms have the intrinsic potential for parallel operations, a traditional computer cannot fully exploit it b ecause of the serial hardware configuration. By using the analog circu it design approach, a large amount of parallel functional units can be realized in a small silicon area. In addition, appropriate accuracy r equirements for neural operation can be satisfied. Components for a ge neral-purpose neural chip have been designed and fabricated. Dynamical ly adjusted weight value storage provides programmable capability. Pos sible reconfigurable schemes for a general-purpose neural chip are als o presented. Test of the prototype neural chip has been successfully c onducted and an expected result has been achieved.