PROBABILITY TO ACHIEVE TSC GOAL

In this paper we propose a probabilistic measure for self-checking (SC ) circuits that is analogous to reliability of fault-tolerant systems. This measure is defined as the probability to achieve totally self-ch ecking (TSC) goal at the tth cycle: TSCG(I). TSCG provides insight to the worst case dynamic behavior of SC circuits with respect to the app lication environment and component failure rates. TSCG surpasses the T SC definitions in determining the applicability of a circuit in a give n application environment. An SC circuit achieves TSC goal when no err oneous information or data is propagated beyond the boundary of this c ircuit. TSCG is therefore the probability that this fault confinement mechanism is intact. The SC properties are obtained through adding har dware redundancy to the original digital design. Which means that an S C circuit has a higher failure rate than the original circuit. Further , there are tradeoffs between the level of hardware redundancy, the re liability, and the TSCG. We give several examples in this paper to cle arly demonstrate these tradeoffs for different design environments. Th e proposed probability measure allows designers to choose from cost-ef fective SC designs that are suitable for their specifications. We emph asize that the TSCG is intended to provide a mean of dynamic error han dling performance evaluation of SC designs. The TSC definitions and al ike are still intact, since a cost-effective SC circuit must begin wit h a TSC circuit. The TSCG gives confidence in the use of cost-efficien t error control codes and/or reduction in error handling capability. A nalogous to reliability, the TSCG can be used in product specification s. This is a crucial step toward the practical applications of TSC or CED circuits.