A FLEXIBLE GATE ARRAY ARCHITECTURE FOR HIGH-SPEED AND HIGH-DENSITY APPLICATIONS

A scaleable gate array has been designed in half-micron CMOS for a wid e range of high-speed and high-density applications Transistor size an d position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory, Design benchmarks have de monstrated 2700 gates/mm(2) routed density in a 0.5 mu m TLM CMOS gate array, Compared to previous 5 V 0.7 mu m gate arrays, the new basecel l provides improvements of 2.5x in density and 30% in speed, at 70% lo wer power. NAND-2 delays are 170 ps (FO = 2, 3.3 V). Metal-programmabl e two-port SRAM's feature 3.9 ns typical access times, The new archite cture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions.