LOW-SUPPLY-NOISE LOW-POWER EMBEDDED MODULAR SRAM

A low-noise, low-power embedded modular SRAM is described. A 512 x 15 configuration at 3.3V generates a maximum of 8.2mA/ns dI/dt and consum es 0.24mW/MHz, the lowest power dissipation ever reported for a modula r embedded memory. Results are achieved using a pulsed divided word li ne architecture, with internal cascaded clocks, weak static sensing, l ow-noise buffers and flip-flops and low-noise low-power decoding techn iques, Alternatives in the core cell, sense amplifier and read/write a rchitecture designs are discussed. Circuit details, as well as experim ental and simulation results, are presented.