NOVEL LOW-VOLTAGE BICMOS DIGITAL CIRCUITS EMPLOYING A LATERAL P-N-P BJT IN A P-MOS STRUCTURE

A new BICMOS buffer circuit and its NAND logic gate implementation for low-voltage environments are presented. The circuit, based on a stand ard BICMOS process, employs a lateral p-n-p BJT in a p-MOS structure t o trap a charge during the pull-up cycle and using it to speed up the pull-down cycle. The analysis, simulations and SPICE results are based on the submicron technologies and they are used to confirm the functi onality of the circuit and evaluate its performance. The comparison wi th previous circuits is carried out in terms of speed, output voltage swing and power dissipation. The results show that a large voltage swi ng at a high speed is achievable under 2.2V operation. The BiFET actio n in the BICMOS circuit design has been verified by some experimental results.