The identification of sensitizable paths and the determination of path
delays play key roles in many delay fault testing schemes. In this pa
per we examine a range of gate delay models with respect to their impa
ct on identifying both sensitizable paths and maximum circuit delays i
n combinational logic circuits, We provide recommendations on the ''mi
nimum acceptable'' model for identifying critical paths, and a minimum
acceptable model for determining maximum circuit delays. In particula
r, we recommend against the use of delay models which fail to distingu
ish between rise and fall delays. Such models, including the commonly-
used ''unit-delay'' model, are shown to significantly misrepresent cir
cuit delay behaviour, particularly with respect to critical paths and
long false paths.