BALANCE TESTING AND BALANCE-TESTABLE DESIGN OF LOGIC-CIRCUITS

We propose a low-cost method for testing logic circuits, termed balanc e testing, which is particularly suited to built-in self testing. Conc eptually related to ones counting and syndrome testing, it detects fau lts by checking the difference between the number of ones and the numb er of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily a nalyzed. We present a novel analysis technique which leads to necessar y and sufficient conditions for the balance testability of the standar d single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also form s the basis for design for balance testability (DFBT), a systematic DF T technique that achieves full coverage of SSL faults. It places the u nit under test in a low-cost framework circuit that guarantees complet e balance testability. Unlike most existing DFT techniques, DFBT requi res only one additional control input and no redesign of the underlyin g circuit is necessary. We present experimental results on applying ba lance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.