ANALOG BOUNDARY-SCAN ARCHITECTURE FOR DC AND AC TESTING

Authors
LEE KJ LEE TP WEN RC LIN ZY
Citation
Kj. Lee et al., ANALOG BOUNDARY-SCAN ARCHITECTURE FOR DC AND AC TESTING, Electronics Letters, 32(8), 1996, pp. 704-705
Citations number
6
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
32
Issue
8
Year of publication
1996
Pages
704 - 705
Database
ISI
SICI code
0013-5194(1996)32:8<704:ABAFDA>2.0.ZU;2-4
Abstract
A new mixed-mode boundary scan architecture is developed. The digital part of this architecture complies with the IEEE Std 1149.1. For the a nalogue part, we propose a new boundary scan cell design and define 4 analogue test instructions. The control signals for each instruction a re also described.