ASYNCHRONOUS VLSI ARCHITECTURE FOR ADAPTIVE ECHO CANCELLATION

Authors
MACKEY RP RODRIGUEZ JJ CAROTHERS JD VRUDHULA SBK
Citation
Rp. Mackey et al., ASYNCHRONOUS VLSI ARCHITECTURE FOR ADAPTIVE ECHO CANCELLATION, Electronics Letters, 32(8), 1996, pp. 710-711
Citations number
6
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
32
Issue
8
Year of publication
1996
Pages
710 - 711
Database
ISI
SICI code
0013-5194(1996)32:8<710:AVAFAE>2.0.ZU;2-A
Abstract
A single chip, 128 coefficient, asynchronous echo canceller is present ed. Cancellation is performed by an FIR filler whose coefficients are adapted using the pourer-of-two modified LMS generates the filtered ou tput every cycle while allowing a sampling rate >206.5 kHz.