OPTIMIZING POWER IN ASIC BEHAVIORAL SYNTHESIS

Citation
R. Sanmartin et Jp. Knight, OPTIMIZING POWER IN ASIC BEHAVIORAL SYNTHESIS, IEEE design & test of computers, 13(2), 1996, pp. 58-70
Citations number
10
Categorie Soggetti
Computer Sciences","Computer Science Hardware & Architecture
ISSN journal
07407475
Volume
13
Issue
2
Year of publication
1996
Pages
58 - 70
Database
ISI
SICI code
0740-7475(1996)13:2<58:OPIABS>2.0.ZU;2-A
Abstract
Attacking power consumption at the behavioral level exploits an applic ation's inherent parallelism to maintain performance while compensatin g for slower, less power-hungry operators. The authors' method and too l optimize and evaluate the effects of power-saving strategies on perf ormance and silicon area.