A 286MM(2) 256MB DRAM WITH X32 BOTH-ENDS DQ

This paper describes a 256 Mb DRAM chip architecture which provides up to x32 wide organization, In order to minimize the die size, three ne w techniques: an exchangeable hierarchical data line structure, an irr egular sense amp layout, and a split address bus with local redrive sc heme in the both-ends DQ were introduced, A chip has been developed ba sed on the architecture with 0.25 mu m CMOS technology, The chip measu res 13.25 mm x 21.55 mm, which is the smallest 256 Mb DRAM ever report ed, A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85 degrees C, In addition, a 100 MHz x32 page mode operation, namely 400 M byte/s data rate, in the standard extende d data output (EDO) cycle has been successfully demonstrated.