PERTURBATION TECHNIQUES FOR ON-CHIP LEARNING WITH ANALOG VLSI MLPS

`Microelectronic neural network technology has become sufficiently mat ure over the past few years that reliable performance can now be obtai ned from VLSI circuits under carefully controlled conditions (see Refs . 8 or 13 for example). The use of analogue VLSI allows low power, are a efficient hardware realisations which can perform the computationall y intensive feed-forward operation of neural networks at high speed, m aking real-time applications possible. In this paper we focus on impor tant issues for the successful operation and implementation of on-chip learning with such analogue VLSI neural hardware, in particular the i ssue of weight precision. We first review several perturbation techniq ues which have been proposed to train multi-layer perceptron (MLP) net works. We then present a novel error criterion which performs well on benchmark problems and which allows simple integration of error measur ement hardware for complete on-chip learning systems.