FULLY PARALLEL INTEGRATED CAM RAM USING PRECLASSIFICATION TO ENABLE LARGE CAPACITIES/

Many applications would benefit from the availability of large-capacit y content addressable memories (CAM's). However, while RAM's, EEPROM's , and other memory types achieve ever-increasing per-chip bit counts, CAM's show little promise of following suit, due primarily to an inher ent difficulty in implementing two-dimensional decoding. The serialize d operation of most proposed solutions is not acceptable in speed-sens itive environments. In response to the resulting need, this paper desc ribes a fully-parallel (single-clock-cycle) CAM architecture that uses the concept of ''preclassification'' to realize a second dimension of decoding without compromising throughput, As is typically the case, e ach CAM entry is used as an index to additional data in a RAM. To achi eve improved system integration, the preclassified CAM is merged into the same physical array as its target RAM, and both use the same core cells. Architecture and operation of the resulting novel memory are de scribed, as are two critical-path circuits: the match-line pull-down a nd the multiple match resolver. The memory circuits, designed in 0.8 m u m BiCMOS technology, may be employed in chips as large as 1 Mb, and simulations confirm 37 MHz operation for this capacity. To experimenta lly verify the feasibility of the architectural and circuit design, an 8 kb test chip was fabricated and found to be fully functional at clo ck speeds up to 59 MHz, with a power dissipation of 260 mW at 50 MHz.