POWER DISSIPATION ANALYSIS AND OPTIMIZATION OF DEEP-SUBMICRON CMOS DIGITAL CIRCUITS

This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circui ts. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minim ize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the su pply voltage, the threshold voltage, and eta, which reflects the drain induced barrier lowing, are also addressed.