SPACE-TIME MAPPING, LATENCY OF DATA-FLOW AND CONCURRENT ERROR-DETECTION IN SYSTOLIC ARRAYS

The problem of mapping a general iterative algorithm with nonunit incr ement/decrement steps of the loop indices onto a systolic array using space-time transformation is studied. Necessary and sufficient conditi ons for the existence of such a space-time mapping are presented. The latency of a systolic computation is characterised in terms of the spa ce-time mapping and the increment/decrement step size of the iterative algorithm. Formulas for the latency of linear and 2D systolic arrays are derived. An efficient space-time mapping using restricted row oper ations which guarantees unit latency, thereby maximising the utilisati on of the processors, is also proposed. Necessary and sufficient condi tions under which column operations can be used to derive a legitimate space-time mapping are presented. A theory relating concurrent error detection and space-time mapping in systolic arrays is proposed. Based on this theory, existing (ad hoc) concurrent error detection approach es can be explained.