A HIGH-SPEED HIGH-DENSITY ARRAY-MULTIPLIER-ACCUMULATOR FOR DIGITAL SIGNAL-PROCESSING

This paper discusses the downsizing and speed improvement of short-wor d multiplier-accumulators, which are frequently used in digital signal processors. As a first step, the optimal configuration for an array-t ype carry-save adder is considered where the shortest path in the full -adder is used to propagate the sum signal and the carry signal is sen t to the full-adder of the two lower stages by skipping a stage. A con figuration of the full-adder suitable for the structure is proposed. T he case of eight partial product additions shows that the delay can be reduced by 22 percent compared to a simple array-type carry-save adde r. Then the short-word carry look-ahead adder using the pass-transisto r logic is considered. It is shown that a single-stage carry look-ahea d circuit with a four-bitwise iterative structure exhibits nearly the same delay as a two-stage carry look-ahead circuit. In other words, th e former is better suited to downsizing. This paper intends to examine the effectiveness of the foregoing new array-type carry-save adder an d the single-stage carry look-ahead circuit using the 0.5-mu m CMOS te chnology. A 16-bit x 14-bit + 31-bit multiplier-accumulator has been d esigned and is evaluated for cases where the array-type carry-save add er is used to handle accumulation as well as partial products. The res ulting area and delay are 0.77 x 0.78 mm(2) and 6.8 ns, respectively. The effectiveness of the approach used in this paper is evaluated by c onstructing a multiplier-accumulator, but the method is also useful in constructing a multiplier.