A GHZ MOS ADAPTIVE PIPELINE TECHNIQUE USING MOS CURRENT-MODE LOGIC

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter devia tions and for operating-environment variations. This technique can als o compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applie d to a 0.4-mu m MOS 1.6-V 1-GHz 64-bit double-stage pipe-line adder, a nd this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by t he control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable f or a few-noise variable delay circuit, Measurement results show that j itter of MCML circuits is about 65% that of CMOS circuits.