Yy. Chai et Lg. Johnson, A 2X2 ANALOG MEMORY IMPLEMENTED WITH A SPECIAL LAYOUT INJECTOR, IEEE journal of solid-state circuits, 31(6), 1996, pp. 856-859
Using floating gate MOSFET's, we have designed a 2 x 2 analog memory,
which is expandable to any size array. The reduced programming voltage
due to the innovative floating gate MOSFET's enables us to construct
the analog memory with a standard double poly n-well process. In addit
ion, a novel programming algorithm is presented, This method will cont
ribute not only to a reduced total programming time, but also to a pro
longed lifetime of the memory. The high voltage program/erase poises a
re arranged to minimize the disturbance of nonselected cells. The reso
lution of a memory cell has been found to be 10 mV over a range of 1.2
5 V to 2 V which is equivalent to the information content of 6 digital
cells.