A PROGRAMMABLE FIR DIGITAL-FILTER USING CSD COEFFICIENTS

An area-efficient programmable FIR digital filter using canonic signed -digit (CSD) coefficients was implemented that uses a switchable unit- delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The proto-type chip can allocate up to 16 pairs o f nonzero CSD coefficient digits for a linear-phase filter, thus reali zing filters with 32 linear-phase taps operating at 180 MHz with two n onzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length an d a reduced data-rate, The chip was implemented with 16-bit IIO in a d ie size of 5.9 mm by 3.4 mm using 1.0-mu m CMOS technology.