F. Dartu et al., PERFORMANCE COMPUTATION FOR PRECHARACTERIZED CMOS GATES WITH RC LOADS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(5), 1996, pp. 544-553
For efficiency, the performance of digital CMOS gates is often express
ed in terms of empirical models. Both delay and short-circuit power di
ssipation are sometimes characterized as a function of load capacitanc
e and input signal transition time. However, gate loads can no longer
be modeled by purely capacitive loads for high performance CMOS due to
the RC metal interconnect effects, This paper presents a methodology
for interfacing empirical gate models to reduced order RC interconnect
models in terms of a nonlinear iteration procedure. The delay and pow
er are calculated with errors on the same order as those for the origi
nal empirical equations. Moreover, a linear equivalent gate model is g
enerated which accurately captures the delays at the interconnect fan-
out nodes.