EPI REPLACEMENT IN MANUFACTURING USING MEV IMPLANTATION

Using MeV ion implantation and Ct bulk wafer denuding/gettering techni ques, we have demonstrated superior latch-up performance and equivalen t silicon surface quality (gate oxide integrity and junction leakage c urrent) to that of p/p(+) epi wafers. Bulk (non-epi) wafers have direc tly replaced epi wafers in manufacturing. Latch-up performance was com pared for epi, retrograde wells, buried layers and buried implanted la yer for lateral isolation structures. Up to a 30x reduction in lateral current gain (BL) was achieved, giving a 5x increase in n(+) trigger current at <2.0-mu m n(+) to p(+) spacing. Epi quality bulk Ct wafer s urfaces have been achieved by optimizing pre-process and process-induc ed denuding and gettering. Up to 16% reduction in total CMOS process c ycle time/complexity can be realized, for a cost savings of >$229 for each 200-mm wafer [1]. This paper describes the advantages and limitat ions of the various MeV epi replacement alternatives from a production point of view.