PROCESS SYNTHESIS AND DESIGN FOR MULTICHIP-MODULE FABRICATION

Multi-Chip Modules (MCM) are an area where process synthesis and sched uling are essential to lowering their production cost. At the present time, MCMs are too expensive except for; high-end applications such as military or supercomputer hardware. The goal of this paper is to outl ine the various processing and testing steps for MCM manufacturing usi ng a State-Task Network (STN), and describe the formulation of the opt imization and scheduling problems for a sub-process. The final portion will describe an example of the use of the STN and optimization model to produce an MILP formulation of both electroless and electroplating copper deposition at fixed processing conditions.