Based on the design of [1], an improved low powered, high gain amplifi
er for capacitive detector front-end read-out is discussed. The optimi
sed amplifier's 1/\f\(alpha) noise is strongly suppressed. The circuit
has a differential gain of >500mV/4fC, an average 10/90% rise time of
150ns (with C-t = 8pF), a noise figure of 562+28.C-t [Note 1] electro
ns (e) over tilde, and a power consumption of 650 mu W. The circuit wa
s simulated in the radiation hard SOI BiCMOS technology of DMILL.