SERENDIPITOUS SEU HARDENING OF RESISTIVE LOAD SRAMS

High and low resistive load versions of Micron Technology's MT5C1008C (128K x 8) and MT5C2561C (256K x 1) SRAMs were tested for SEU vulnerab ility. Contrary to computer simulation results, SEU susceptibility dec reased with increasing resistive load. A substantially larger number o f multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a ''1'' --> ''0'' to ''0'' --> ''1'' bit error ra tio close to unity; in contrast, the high resistive load devices displ ayed a pronounced error bit polarity effect. Two distinct upset mechan isms are proposed to account for these observations.