A FLEXIBLE ANALOG MEMORY ADDRESS LIST MANAGER FOR PHENIX

A programmable analog memory address list manager has been developed f or use with all analog memory-based detector subsystems of PHENIX. The unit provides simultaneous read/write control, cell write-over protec tion for both a Level-1 trigger decision delay and digitization latenc y, and re-ordering of AMU addresses following conversion, at a beam cr ossing rate of 105 ns. Addresses are handled such that up to 5 Level-1 (LVL-1) events can be maintained in the AMU without write-over. Data tagging is implemented for handling overlapping and shared beam-event data packets. Full usage in all PHENIX analog memory-based detector su bsystems is accomplished by the use of detector-specific programmable parameters - the number of data samples per valid LVL-1 trigger and th e sample spacing. Architectural candidates for the system are discusse d with emphasis on implementation implications. Details of the design are presented including application specifics, timing information, and test results from a full implementation using field programmable gate arrays (FPGAs).