THE RD27 MUON TRIGGER CO-INCIDENCE ARRAY DEMONSTRATOR ASIC

One aim of the RD27 project is to perform design and R&D work leading to a first level muon trigger for an experiment at the Large Hadron Co llider (LHC) at CERN. This paper describes the design, implementation and testing of an ASIC for a trigger demonstrator system. The trigger system is implemented using a set of seven chambers. The low momentum trigger requires hits in three out of the four inner chambers. The hig h momentum trigger requires a low momentum trigger and hits in two of three outer chambers. This scheme allows for chamber inefficiencies fo r real muons and reduces the trigger rate from neutron and photon-indu ced background in the detectors. The core of the ASIC is an eight by t wenty-four input 'double' co-incidence array allowing two momentum cut s to be applied. The ASIC has multiple inputs per axis and includes th e multiplicity logic. The design of the ASIC is flexible enough to dem onstrate fully combinatorial operation, fully pipelined operation, or any combination of the two. The ASIC has been fabricated using a 34k g ate, 0.5 mu m CMOS gate army from Fujitsu. Testing confirms it can be pipelined at above 100MHz or fully combinatorial with a measured maxim um propagation delay of 7.4ns, varying by up to 2ns depending on input pattern.