We describe a general purpose 40MHz pipelined trigger processing board
containing six look-up tables and the logic needed to programmably ro
ute the signals between them. A series of identical boards are connect
ed in cascade in the NA48 CP-violation experiment at CERN, accept digi
tal inputs generated from calorimeter signals and are used to perform
the different computations necessary for the trigger reconstruction. T
he board architecture is designed to be flexible so that a single basi
c hardware design can perform all the different algorithms we require
and so that the trigger algorithms can be adapted if needed. The compu
tation latency of the combined network of eight boards is approximatel
y 3 mu s. We present examples of some of the functions which have been
implemented. We discuss the automatic reprogramming software which ha
s been developed so that a new design can be implemented easily.