A MONOLITHIC, CONSTANT-FRACTION DISCRIMINATOR USING DISTRIBUTED R-C DELAY-LINE SHAPING

A monolithic, CMOS, constant-fraction discriminator (CFD) was designed and fabricated in a 1.2-mu, N-well process. This circuit used an on-c hip, distributed R-C delay line to realize the constant-fraction shapi ng. The delay line was constructed of a 4.8-mu wide, 500-mu long serpe ntine layer of polysilicon above a grounded second layer of polysilico n. This line generated about 1.1 ns of delay for a 5-ns risetime signa l with a slope degradation of only 15%. The CFD also featured de feedb ack for both the arming and zero-crossing discriminators to eliminate timing errors caused by offsets. The entire circuit, including the del ay line, required an area of 200 mu x 950 mu. The timing walk for 5-ns risetime signals over the dynamic range from -20 mV to -2 V was less than +/- 150 ps. Each channel of the CFD consumed similar to 15 mW fro m a single 5-V supply.