A CMOS DELAY LOCKED LOOP AND SUBNANOSECOND TIME-TO-DIGITAL CONVERTER CHIP

Phase-locked loops have been employed in the past to obtain sub-nanose cond time resolution in high energy physics and nuclear science applic ations. An alternative solution based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration y et still offers resolution in the sub-nanosecond regime. Two variation s on this solution are outlined. A novel phase detector, based on the Muller C-element, is used to implement a charge pump where the injecte d charge approaches zero as the loop approaches lock on the leading ed ge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout gene rators are used to automatically layout a highly integrated, multichan nel time-to-digital converter (TDC) targeted for one specific frequenc y. The two circuits, DLL and TDC, are implemented in CMOS 1.2 mu m and 0.8 mu m technologies, respectively. Test results show a timing jitte r of less than 30 ps for the DLL circuit and less than 190 ps integral and differential non-linearity for the TDC circuit.