REDUCED MULTIPIPELINE MACHINE DESCRIPTION THAT PRESERVES SCHEDULING CONSTRAINTS

High performance compilers increasingly rely on accurate modeling of t he machine resources to efficiently exploit the instruction level para llelism of an application. In this paper, we propose a reduced machine description that results in faster detection of resource contentions while preserving the scheduling constraints present in the original ma chine description. The proposed approach reduces a machine description in an automated, error-free, and efficient fashion. Moreover, it full y supports schedulers that backtrack and process operations in arbitra ry order. Reduced descriptions for the DEC Alpha 21064, MIPS R3000/R30 10, and Cydra 5 result in 4 to 7 times faster detection of resource co ntentions and require 22 to 90% of the memory storage used by the orig inal machine descriptions. Precise measurement for the Cydra 5 indicat es that reducing the machine description results in a 2.9 times faster contention query module.