TOWARDS A HIGH-LEVEL POWER ESTIMATION CAPABILITY

We will present a power estimation technique for digital integrated ci rcuits that operates at the register transfer level (RTL). Such a high -level power estimation capability is required in order to provide ear ly warning of any power problems before the circuit-level design has b een specified. With such early warning, the designer can explore desig n trade-offs at a higher level of abstraction than previously possible , reducing design time and cost. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the fin al implementation of a circuit, given only its Boolean functional desc ription. This technique has been implemented and tested on a variety o f circuits, The empirical results to be presented are very promising a nd demonstrate the feasibility and utility of this approach.