TRANSISTOR SIZING FOR LOW-POWER CMOS CIRCUITS

A direct approach to transistor sizing for minimizing the power consum ption of a CMOS circuit under a delay constraint is presented. In cont rast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active a rea. Analytical formulation for the power dissipation of a circuit in terms of the transistor size is derived which includes both the capaci tive and the short circuit power dissipation. SPICE circuit simulation results are presented to confirm the correctness of the analytical mo del. Based on the intuitions drawn from the analytical model, heuristi cs for initial transistor sizing on critical and noncritical paths for minimum power consumption are developed. Further, fast heuristics to perform transistor sizing in CMOS circuits for minimizing power consum ption while meeting the given delay constraints are presented.