J. Craninckx et Msj. Steyaert, A 1.75-GHZ 3-V DUAL-MODULUS DIVIDE-BY-128/129 PRESCALER IN 0.7-MU-M CMOS/, IEEE journal of solid-state circuits, 31(7), 1996, pp. 890-897
A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7
-mu m CMOS technology, A new circuit technique enables the limitation
of the high-speed section of the prescaler to only one divide-by-two f
lipflop. In that way, a dual-modulus prescaler with the same speed as
an asynchronous divider can be obtained, The measured maximum input fr
equency of the prescaler is up to 2.65 GHz at 5 V power supply voltage
, Running at a power supply of 3 V, the circuit consumes 8 mA at a max
imum input frequency of 1.75 GHz.