2.5 V CMOS CIRCUIT TECHNIQUES FOR A 200 MHZ SUPERSCALAR RISC PROCESSOR

Novel 2.5 V CMOS circuit techniques including a noise tolerant prechar ge (NTP) circuit and a leakless buffer circuit are applied to a floati ng point macrocell for a 200 MHz superscalar RISC processor, The NTP c ircuit has two advantages: high noise immunity and high speed, Floatin g point operations can be executed in a two cycle latency using the hi gh speed NTP circuit, The leakless buffer circuit with NMOS transmissi on gate in 128 floating point registers makes possible both high integ ration and low power dissipation, since the circuit causes no leak cur rent without precharging the number of read lines, The processor makes use of 0.3-mu m CMOS technology with a 2.5 V power supply and four me tal layers, The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS.