OFFSET-TRIMMING BIT-LINE SENSING SCHEME FOR GIGABIT-SCALE DRAMS

A new offset-trimming bit-line sensing scheme is described which is su itable for Gigabit-scale DRAM's, This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter varia tion of deep submicron transistors, The effective offset voltage depen dence on trimming time is analyzed and verified with simulation result s, As compared With a conventional direct sensing scheme, the proposed scheme shows remarkable improvement on the sensitivity, A test device was fabricated with a 0.25 mu m CMOS technology and its measurement r esults indicate the successful operation of offset-trimming.