A MULTIPLIER-ACCUMULATOR MACRO FOR A 45MIPS EMBEDDED RISC PROCESSOR

This paper describes a high speed and area effective multiplier-accumu lator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth's encoder twice in a cycle, T he multiplier-accumulator executes one multiply-add operation (32 b mu ltiplication followed by 64 b addition) per cycle at 56.5 MHz. The are a is 2.35 mm(2) with 0.4 mu m CMOS technology.