PROCESS COMPILATION OF THIN-FILM MICRODEVICES

This paper describes a systematic method for the automatic generation of fabrication processes of thin film devices, The method uses a parti ally ordered set (poset) representation of device topology describing the order between its various components in the form of a directed acy clic graph, The sequence in which these components are fabricated is d etermined from the poset linear extensions, and the component sequence is expanded into a corresponding process flow, The graph-theoretic sy nthesis method is powerful enough to establish existence and multiplic ity of flows thus creating a design space D suitable for optimization, The cardinality \\D\\ for a device with N components is large with a worst case \\D\\ less than or equal to (N - 1)! yielding in general a combinatorial explosion of solutions. The number of solutions is contr olled through a priori estimates of \\D\\ and condensation of the devi ce graph, The method has been implemented in the computer program MIST IC (Michigan Synthesis Tools for Integrated Circuits) which calculates specific process parameters using an internal database of process mod ules and materials, Currently, MISTIC includes process modules for dep osition, lithography, etching, ion implantation, coupled simultaneous diffusions, and reactive growth. The compilation procedure was applied to several device structures, For a double metal twin-well BiCMOS str ucture, the compiler generated 168 complete process flows.