LAYOUT TO CIRCUIT EXTRACTION FOR 3-DIMENSIONAL THERMAL-ELECTRICAL CIRCUIT SIMULATION OF DEVICE STRUCTURES

In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behav ior, The networks represent a three-dimensional (3-D) device structure with circuit elements, The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator, S patial potential distributions, current flows, and temperature distrib utions in the device structure are calculated on the spatial coordinat es, This simulation method can be placed between device simulation and (conventional) circuit simulation, It has been implemented in a circu it simulator and is demonstrated for simulation of self-heating in a b ipolar low frequency power transistor, The main advantage of this simu lation method Is that not only the 3-D thermal behavior of the whole c hip is simulated, but that this is also directly coupled to the electr ical device behavior by means of the power dissipation and temperature distribution in the device, This offers the possibility for the circu it designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator, As an example, the influence of the emitter cont acting on the internal temperature and current distribution of a BJT i s investigated.