MODELING AND SIMULATION OF BROKEN CONNECTIONS IN CMOS ICS

This paper presents a fault model, called node-break fault model, to e ffectively account for broken connections inside CMOS circuits. The pr oposed model is very general since it allows to generate test vectors for broken connections that cannot be detected by means of test sequen ces for stuck-open faults. In addition, the detection of a broken conn ection in a node ensures the detection of all stuck-open faults of the transistors connected to that node, thus superseding the stuck-open f ault model, The model can be used to derive tests and to perform fault simulations independent of the actual layout of the circuit. Conditio ns for the detection of broken connections are derived from electrical considerations (aimed at verifying the presence of electrical continu ity between the terminals of transistors connected to a node) while th e minimum number of input vectors to test for broken connections in a node is determined by graph theory. Fault simulations performed on ben chmark circuits using test sequences oriented to the detection of stuc k-open faults show their inadequacy in detecting node-break faults, th us claiming for considering such a fault model in the test pattern gen eration.