FUNCTIONAL TEST-GENERATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS

We present a novel, highly efficient functional test generation method ology for synchronous sequential circuits. We generate test vectors fo r the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinat ional and sequential circuits, synthesized through algebraic transform ations. The truth table of the combinational logic of the circuit is m odeled in the form known as personality matrix (PM) and vectors are ob tained using highly efficient cube-based test generation method of pro grammable logic arrays (PLA). Sequential circuits are modeled as array s of time-frames and new algorithms for state justification and fault propagation through faulty PLA's are derived. We also give a fault sim ulation procedure for G and D faults. Experiments show that test gener ation can be orders of magnitude faster and achieves a coverage of gat e-level stuck faults that is higher than a gate-level sequential-circu it test generator, Results on a broad class of small to large synthesi s benchmark FSM's from MCNC support our claim that functional test gen eration based on G and D faults is a viable and economical alternative to gate Level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obt ained even when details of specific implementation are unavailable. Fo r the ISCAS'89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of th ese tests.