111-MHZ 1-MBIT CMOS SYNCHRONOUS BURST SRAM USING A CLOCK ACTIVATION CONTROL METHOD

This paper reports a 32 k x 32 1-Mbit CMOS synchronous pipelined burst SRAM. A clock access time of 3.6 ns and a minimum cycle time of 9 ns (111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 mu A were successfully realized. These results can be obtained by a new activation control method in which th e internal clock pulses control the decoders, the low resistive bit li ne and memory cell GND line and the optimization of write recovery tim ing and data sense timing.