A 4-MB SRAM USING A NEW HIERARCHICAL BIT-LINE ORGANIZATION UTILIZING A T-SHAPED BIT-LINE FOR A SMALL-SIZED DIE

This paper describes a new hierarchical bit line organization utilizin g a T-shaped bit line (H-BLT) and its practical implementation in a 4- Mb SRAM using a 0.4 run CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple block-division of the memory cell array. The size of the SRAM die was reduced by 14% without an access p enalty. The active current is 30 mA at 5 V and 10 MHz. The typical add ress access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the fut ure.