CACHE WRITE GENERATE FOR PARALLEL IMAGE-PROCESSING ON SHARED-MEMORY ARCHITECTURES

Authors
WITTENBRINK CM SOMANI AK CHEN CH
Citation
Cm. Wittenbrink et al., CACHE WRITE GENERATE FOR PARALLEL IMAGE-PROCESSING ON SHARED-MEMORY ARCHITECTURES, IEEE transactions on image processing, 5(7), 1996, pp. 1204-1208
Citations number
10
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE transactions on image processing → ACNP
ISSN journal
10577149
Volume
5
Issue
7
Year of publication
1996
Pages
1204 - 1208
Database
ISI
SICI code
1057-7149(1996)5:7<1204:CWGFPI>2.0.ZU;2-D
Abstract
We investigate cache write generate, our cache mode invention. We demo nstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluate d.