The drain-induced-barrier-lowering (DIBL) considerations of the extend
ed drain structure were studied using two-dimensional (2-D) device sim
ulations in the tenth-micrometer regime. We found that the drain exten
sion length must be kept at a minimum in order to reduce the transisto
r cell area and to improve the device transconductance, G(m). However,
without decreasing the deep source/drain junction depth, the minimum
value of which is basically limited by the ability to form a good low
resistive silicide contact, charge sharing associated with a small ext
ension length deteriorates the short channel behavior of the device, v
ia DIBL, even if aggressive scaling of the gate oxide thickness and th
e junction depth of the drain extension were used, The solution to thi
s dilemma would be elevating the source/drain area by selective epitax
y to form a shallow, low resistive silicided junction. We propose here
a novel device structure using the elevated silicide-as-a-diffusion-s
ource (E-SADS), which improves the DIBL-G(m) tradeoff, eliminates the
contact problem, and maintains a minimal cell areal increase.