T. Ikedo, DESIGN AND PERFORMANCE EVALUATION OF A PIXEL CACHE IMPLEMENTED WITHINAPPLICATION-SPECIFIC INTEGRATED-CIRCUITS, The visual computer, 12(5), 1996, pp. 215-233
The application-specific integrated circuit (ASIC) design and the perf
ormance of a graphics processor that uses a pipelined-cache with FIFO
memory to transfer a 3D pixel array and its z values to the frame buff
er in one cycle are described in detail. The functional modules in the
graphics processor include: (1) a video refresh converter, (2) a modu
le that combines texture-mapped patterns onto Phong-shaded surfaces, a
nd (3) a bidirectional parallel link between external devices and the
frame-buffer modules. Digital differential analyzer (DDA) algorithms a
nd the size of the pixel cache relative to the frame-buffer bandwidth,
have been selected for good overall performance. A drawing speed of 8
ns/pixel (32 bits/pixel) or 1.2 million Phong-shaded polygons/s (100-
pixel polygons, texture mapped with hidden surface removal) was achiev
ed when 60-ns access-time single port DRAMs and synchronous DRAMs were
used.